1. Field of the Invention
The invention relates to addressing systems. Specifically, the invention relates to apparatus, systems, and methods to avoid address conflicts between slave devices sharing a common physical address and communicating with a host device over an I2C bus.
2. Description of the Related Art
Widespread acceptance and success of the Inter-Integrated Circuit bus (“I2C bus”) has emerged as a result of its simplicity of design and protocol format. Originally developed to connect a CPU to peripheral chips in a television set, the I2C bus is a simple bi-directional two-wire interface that provides efficient inter-integrated circuit (“IC”) control. Physically, the I2C bus includes two active wires, a serial data line (“SDA”) and a serial clock line (“SCL”). As both active wires are “open drain” drivers, a set of pull-up resistors may be implemented to enable each line to be pulled high as needed.
The I2C interface is a simple master/slave type interface where the maximum number of slave devices connected to the I2C bus is dictated by the maximum allowable capacitance on the lines, as well as by the protocol's addressing limit. Typically, the I2C bus includes one master and multiple slave devices, though a multi-master system is possible. In any case, any device on the bus may act as a receiver and/or transmitter depending on its functionality, although only the master initiates and controls the data transfer.
According to standard I2C operation, the master device initiates communication with a slave device by placing a start sequence on the bus, followed by an address uniquely corresponding to the slave device. In this manner, all slave devices are initially alerted to incoming data, but only the device having an address matching the transmitted address communicates with the master device.
Servers typically implement numerous I2C slave devices to perform various functions, including hardware monitors, clock generators, in/out (“I/O”) devices, and memory storage devices such as random access memory (“RAM”) and selectrically erasable programmable read-only memory (“EEPROM”). A problem often arises, however, when more than one of the same slave device is plugged into one chassis. Each slave device in a server chassis generally contains an EEPROM storing serial numbers and field replaceable unit (“FRU”) information. Most off-the-shelf EEPROMs, however, reside in the same 8-bit addressing range, 0xA0-0xAF, for example. Accordingly, multiple identical slave devices incorporating off-the-shelf EEPROMs typically share a single common address.
For example, more than one Ethernet Switch Module may be plugged into the same IBM® eServer® BladeCenter™ unit. In such a case, multiple Ethernet Switch Modules, each identified by a single common address, may be put on the same I2C bus. As a result, data destined for a particular Ethernet Switch Module may be inadvertently received by another Ethernet Switch Module, thus compromising accurate and efficient data transmission.
One solution to this problem is to implement multiple I2C buses, each bus corresponding to exactly one multiple device. In this manner, each multiple device is independently and uniquely recognized by its corresponding bus. While effective to avoid address conflicts between multiple devices, this solution multiplies both the costs and components necessary for I2C data transfer between a host device and multiple identical slave devices. Other solutions include various methods of dynamic addressing, such as implementing multiplexors to reside on a single I2C bus common to the multiple devices. These solutions, however, complicate the software needed to access each of the multiple devices while increasing data transfer time as well as associated costs.
From the foregoing discussion, it should be apparent that a need exists for an apparatus, system, and method to avoid address conflicts between multiple slave devices communicating with a host device over a single I2C bus. Beneficially, such an apparatus, system, and method would increase efficient and reliable I2C data transfer from the host device to an intended slave device while minimizing costs and complexities associated with dynamic I2C addressing techniques and other prior art solutions. Such an apparatus, system, and method is disclosed and claimed herein.